1. Field of the Invention
The present invention relates to a power-save control for an information processing apparatus, an electrical apparatus, a clock controlling method for the information processing apparatus, a clock controlling program and a program product. More particularly, the present invention relates to a technology for reducing power consumption by controlling a clock frequency.
2. Description of the Related Art
There is a large demand to suppress power consumption to a lower level in existing household apparatus such as mobile phones, mobile audio equipments and digital cameras. Many processors including a CPU (central processing unit) are incorporated into existing household apparatus. Power consumption tends to increase since many software applications operate simultaneously in these processors, and a display or display device that consumes a large amount of power is provided. Thus, technology for suppressing power consumption has come to be required.
A technology for controlling a clock frequency, which is the frequency of a clock fed to the information processing apparatus, in accordance with a state of the information processing apparatus, has been known as a technology for suppressing power consumption by an information processing apparatus. One of such known prior art technologies is such that the frequency of a clock specially fed to a CPU, which normally operates at a lower clock frequency, is increased only during an external interrupt period and a succeeding specific period (for example, see Japanese Unexamined Patent Publication No. H05-108191). According to this technology, the clock frequency is controlled by referring to hardware on a device whose interrupt flag is set.
There is also known a technology according to which minimum performances required by tasks are set as prerequisites, and are set in a setting circuit so that a clock frequency is controlled in accordance with the performances upon activating each task (for example, see Japanese Unexamined Patent Publication No. H08-76874).
There is further known a technology of constantly preparing a task of decreasing a clock frequency with a lowest degree of priority in a multi-task operating system (for example, see Japanese Unexamined Patent Publication No. H04-278612). According to this technology, the consumption of power is suppressed by decreasing the clock frequency when the processings of all the other tasks are completed, i.e., when a system enters a standby state.
However, it is necessary to enable the proper operation of the apparatus at the same time that the power consumption of a household apparatus is suppressed, and many of the processors provided in the household apparatuses are required to have a real-time operability. The real-time operability is for guaranteeing that a processing is executed within a specified period after such processing is requested. Since the request of no other processing is received in a section during which an exclusive processing is executed, e.g., in a section during which the execution of other processing is prohibited while a certain processing is being executed, there is a danger of impairing the real-time operability. Therefore, the section during which an exclusive processing is executed has to be as short as possible.
The prior art technology disclosed in Japanese Unexamined Patent Publication No. H05-108191 is designed to increase the clock frequency during the external interrupt period, and presents a problem that the power consumption is always high and no power-save control can be executed in real time during the external interrupt period. The prior art technology disclosed in Japanese Unexamined Patent Publication No. H08-76874 is designed for the control of the clock frequency in accordance with the performances required by the respective tasks, and presents a problem that the performances required by the respective tasks need to be determined and set beforehand. Further, since the prior art technology disclosed in Japanese Unexamined Patent Publication No. H04-278612 is designed to decrease the clock frequency when the processings of all the other tasks are completed, it presents a problem that the power consumption is high until all the other tasks are completed and no power-save control can be executed in real time.